1. Technical Field
The invention relates generally to verification of electronic circuit designs, and particularly to verification of multi-voltage circuit designs.
2. Prior Art
Electronic Design Automation (EDA) is a process which uses computer programs to design, simulate, and test electronic circuits before they are fabricated. Simulating designs with simulation software on emulation systems, and/or using simulation acceleration systems, detects and corrects design flaws before fabrication of the silicon device. Test before fabrication processes save manufacturers millions of dollars in Non-Recoverable Engineering (NRE) costs.
An automated circuit design process includes several steps, beginning with providing a Hardware Description Language (HDL) description (a high level description) of a circuit design. Several HDLs are commonly available, e.g. Verilog and VHDL. The HDL description may also be in the form of a Register Transfer Logic (RTL) code. A computer-implemented process converts the high-level description into a netlist, which is a description of the electronic circuit that specifies what cells compose the circuit and which pins of which cells are to be connected together (“nets”). A netlist does not describe the physical location of the cells on a silicon chip. The netlist creation process is followed by a placement process, which finds a location for each cell on a circuit board or silicon chip. The locations are specified, typically, in two dimensional (i.e., x, y) spatial coordinates on the circuit board or silicon chip. Subsequently, the netlist and the cell location information are used to perform a wire routing process which generates a wire geometry for connecting pins together. This information is converted into a description of a mask for fabrication of the actual silicon chip. The description may be provided in available languages such as GSD2.
After certain stages of the automated circuit designing process, the resulting information needs to be verified. FIG. 1 is a flowchart illustrating the generic method used by automated circuit design tools for verification of circuit designs. Step 102 inputs a Hardware Description Language (HDL) description of the design. The HDL describes the circuit design in blocks and sub-blocks, which may also be referred to as design elements. Each design element may in itself be a semiconductor device, for example a transistor. A design element may also be a combination of two or more semiconductor devices.
Step 104 compiles the HDL description of the circuit design to logically validate the design. A typical compilation process converts the HDL into several design objects. The design objects may correspond to each design element, the voltage connections to the design element, the logical connections between the design elements, and the like. Subsequent to compilation, step 106 performs the simulation process, which applies voltage vectors at the inputs of the circuit design. These voltage vectors result in logic waveforms in the circuit design. The logic waveforms in a digital circuit have certain specific values, for example, 0, 1, X and Z in case of Verilog. The voltage vector values varying with time change the resulting logic waveforms, which are observed and recorded. Step 108 generates the simulation results representing the behavior of the circuit under certain parameters. The behavior is then compared with the expected results from the circuit.
Electronic circuits are becoming increasingly complex and encountering new problems, including that of power management. Today's electronic circuits consume significant amount of power, which is undesirable because of heating problems and limited battery life of electronic devices. Therefore, managing power for optimal use is highly desired.
One way of optimizing power consumption is by designing multi-voltage electronic circuits. In a multi-voltage design, different functional units of the electronic circuit are operated at different voltages at different times. For example, in case of an electronic circuit for a mobile phone, the functional units for audio, processing and camera are different. When the audio unit is being operated, the camera unit may be switched off and the processing unit may be operated at 1.0 V. In another case, when the camera unit is being operated, the audio unit may be switched off and the processing unit may be operated at 1.2 V. A mobile phone circuit design element may have voltage states such as active, standby, sleep, shutdown, etc.
Multi-voltage electronic circuits have complex designs comprising several elements or cells which are characterized by their connections to various power rails carrying different voltages which may change with time.
FIG. 2 is a schematic of an example design element 402 having input 404 and output 406 connections that carry logic waveforms having particular values, for example 0, 1, X or Z in Verilog. Design element 402 is connected to seven voltage rails; a VDD rail 408, a SLPP rail 410, a SLPN rail 412, a VBBP rail 414, a VBBN rail 416, and a VSS rail 418, and VRET rail (not shown in FIG. 2).
VDD rail 408 is a driving rail that provides power to design element 402. SLPP rail 410 and SLPN rail 412 are sleep rails connected to the gates of header transistor 409 and of footer transistor 411 to apply positive, zero, or negative voltage differences between the gate and the source of the transistors and thereby cut off leakage current between rails 408 and 418. VBBP rail 414 and VBBN rail 416 are body bias rails for Positive Metal Oxide Semiconductor (PMOS) transistor 415 and for Negative Metal Oxide Semiconductor (NMOS) transistor 417 respectively, which are applied to the bulk connection and can either be forward or reverse biased to control threshold voltage (Vt).
Other design elements may have connections to fewer or more voltage rails. For example FIG. 4 design elements A, B and C are each connected to only two voltage rails.
The values of voltages on the rails connected to design element 402 determine its voltage state, of which there may be several. An example design element 402 may have five voltage states: active state, shutdown state, standby state, sleep state, and retention state. During the active state, VDD rail 408 operates on an allotted functional voltage value, and design element 402 can perform all its functions. During shutdown state, VDD rail 408 is turned off, but its voltage value is not zero. Standby state is a low power state which expects a quick wakeup. State retention in memory elements of a design element 402 is essential. Typically, in standby state all the clocks are gated, i.e. deactivated by a gating design element such as an AND gate. Standby state may have multiple grades which progressively turn off more circuitry. Entering and leaving standby state involves gradually turning off/on of clocks, PLLs, and voltages. Sleep state is a variation of shutdown state, and is also called power gating. SLPP 410 and/or SLPN 412 are controlled with a negative Vgs (V gate-source) to cut off design element 402 from VDD 408 and/or GND=VSS 418.
However, complex voltage designs of electronic circuits make verification of the designs extremely difficult. The above mentioned process is insufficient for validation of multi-voltage circuit designs. Existing methods for verification of multi-voltage electronic circuit design suffer from one or more of the following problems. First, logic simulators for the verification of multi-voltage electronic circuits are not voltage aware, i.e. they do not consider voltage as a parameter for simulation, although in reality voltage is a key parameter. Therefore, any design simulation without consideration of voltage is susceptible to lead to faulty designs. Second, the existing methods of verification of multi-voltage circuit designs do not provide the required accuracy. Third, the existing simulation methods are slow and therefore require long time to generate results. There exists, therefore, a need for a simulation method that is voltage aware.